Sponsor: IBM Quantum
Context
A key problem in the race for large-scale error-corrected quantum computers, the implementation of quantum error correction code plays a huge role. Recent advances in LDPC
code design have significantly lowered the hardware quality requirements for actual implementation of quantum memories [1, 2].
However, implementation details can still be improved in order to further reduce those requirements. In particular, many operations appearing in the code’s implementation require finding low cost Clifford circuits implementing logical operations of syndrome measurements. In some cases, the processor’s architecture is tailored to induce low cost implementations of those. In other cases, it is still an “open” problem to optimize those circuits.
Recent works show new techniques to efficiently insert spacetime Pauli checks (or “flags”) to detect the presence of errors propagating inside a Clifford circuit [3]. Thanks to the versatility of state-of-the-art decoders, this extra detection information can transparently be used by decoders to improve logical error rate of the resulting quantum memory.
Objectives
The goal of this project is to try and improve the performances of existing logical operations and syndromes measurements in the bicycle LDPC code using these new Pauli checks/flags approach and propose improved chip architectures.
References
[1] High-threshold and low-overhead fault-tolerant quantum memory, Sergey Bravyi, Andrew W. Cross, Jay M. Gambetta, Dmitri Maslov, Patrick Rall & Theodore J. Yoder
[2] Universal adapters between quantum LDPC codes, Esha Swaroop, Tomas Jochym-O'Connor, Theodore J. Yoder
[3] Low-overhead error detection with spacetime codes, S. Martiel and A. Javadi-Abhar